1. Field of the Invention
The present invention relates to the provision of a fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages. Furthermore, the invention also relates to method of producing the fine pitch solder bump structure with built-in stress buffer.
2. Discussion of the Prior Art
In the current state-of-the-technology, extremely important difficulties are encountered in connection with the satisfactory obtention of structures of fine pitch Pb-containing and Pb-free solder bump parts, which are employed in FCPBGA packages, wherein the fine pitch may be approximately 150 μm. These packages are subjected to extremely high stress levels during the implementing of semiconductor chip join operations and associated thermal cycling, which frequently causes interconnect reliability problems and the occurrences of electrical openings or disconnects, which adversely affect the functioning and resultant viability of the manufactured electronic packages.
In particular, with the use of brittle Pb-Free C4 materials, the overall chip package interconnect structure is rigid in nature, and does not possess any suitable capability of relieving these stresses other than by cracking of the solder and/or the underlying dielectric materials on the chip side. Thus, any stresses that are encountered are particularly pronounced in the z-direction. Hereby, any stress induced cracking that is observed, for example, through the application of a Sonoscan has given rise to the term “white bumps”, which is currently instrumented in gating or essentially restricting the successful qualification of critical fine pitch (150 μm) technology products for key customers employing such products.